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This X24645 device has been acquired by IC MICROSYSTEMS from Xicor, Inc.
ICmic
IC MICROSYSTEMS
TM
64K
2
X24645
8192 x 8 Bit
Advanced 2-Wire Serial E PROM with Block LockTM Protection
FEATURES *2.7V to 5.5V Power Supply *Low Power CMOS --Active Read Current Less Than 1mA --Active Write Current Less Than 3mA --Standby Current Less Than 1A *Internally Organized 8192 x 8 *New Programmable Block Lock Protection --Software Write Protection --Programmable hardware Write Protect *Block Lock (0, 1/4, 1/2, or all of the E2PROM array)
DESCRIPTION 2 The X24645 is a CMOS 65,536-bit serial E PROM, internally organized 8192 x 8. The X24645 features a
serial interface and software protocol allowing operation on a simple two wire bus.
Two device select inputs (S1, S2) allow up to four devices to share a common two wire bus. A Write Protect Register at the highest address location, 1FFFh, provides three new write protection features: Software Write Protect, Block Write Protect, and Hardware Write Protect. The Software Write
*2 Wire Serial Interface *Bidirectional Data Transfer Protocol *32 Byte Page Write Mode
Protect feature prevents any nonvolatile writes to the X24645 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user to individually write protect four blocks of the array by
--Minimizes Total Write Time Per Byte *Self Timed Write Cycle --Typical Write Cycle Time of 5ms *High Reliability --Endurance: 100,000 Cycles --Data Retention: 100 Years *Available Packages --8-Lead PDIP --8-Lead SOIC (JEDEC) --14-Lead SOIC (JEDEC) --20-Lead TSSOP FUNCTIONAL DIAGRAM
WP
programming two bits in the write protect register. The Programmable Hardware Write Protect feature allows
the user to install the X24645 with WP tied to VCC, program the entire memory array in place, and then enable the hardware write protection by programming a WPEN bit in the write protect register. After this, selected blocks of the array, including the write protect register itself, are permanently write protected, as long
as WP remains HIGH.
START CYCLE
V CC V SS
H.V. GENERATION TIMING &
CONTROL
SDA
START STOP
WRITE PROTECT REGISTER AND
LOGIC
LOGIC
CONTROL LOGIC SLAVE ADDRESS REGISTER
SCL
+COMPARATOR
LOAD
INC
XDEC
E PROM 256 X 256
2
S 2 S 1
WORD ADDRESS COUNTER
R/W
YDEC 8 CK PIN DATA REGISTER
D OUT
D OUT ACK
2783 ILL F01
(c)Xicor, 1995, 1996 Patents Pending 2783-3.5 5/13/96 T1/C0/D0 NS
1
Characteristics subject to change without notice
X24645
ICmic E PROMs are designed and tested for applications requiring extended endurance. Inherent data
2
PIN CONFIGURATIONS
8-LEAD DIP & SOIC NC
1 2 3 4 8 7 6 5
V CC
retention is greater than 100 years.
PIN DESCRIPTIONS Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and
S 1 S 2 V SS
X24645
WP SCL SDA
14-LEAD SOIC NC NC
V CC
may be wire-ORed with any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet. Device Select (S1, S2) The device select inputs (S1, S2) are used to set the first and second bits of the 8-bit slave address. This allows up to four X24645 devices to share a common bus. These inputs can be static or actively driven. If
used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with
NC NC
1 2 3 4 5 6
14 13 12 X24645 11
NC
S 1 S 2
V SS NC
7
10 9 8
WP SCL SDA
NC
20-LEAD TSSOP
NC NC
S 1 NC NC
1 2 3 4
20 19
NC
V CC
18 17 X24645 16 15 14 13 12 11
WP NC NC NC
CMOS levels (driven to VCC or VSS).
Write Protect (WP) The write protect input controls the hardware write protect feature. When held LOW, hardware write protection is disabled and the X24645 can be written normally. When this input is held HIGH, and the WPEN
5 6 7 8 9 10
NC
S 2 V SS
SCL SDA
NC NC
NC NC
2783 ILL F02.4
bit in the write protect register is set HIGH, write protection is enabled, and nonvolatile writes are
disabled to the selected blocks as well as the write protect register itself.
PIN NAMES Symbol
S1, S2 SDA SCL WP VSS VCC NC
Description
Device Select Inputs Serial Data Serial Clock Write Protect Ground Supply Voltage No Connect
2783 FRM T01.1
2
X24645
DEVICE OPERATION The X24645 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24645 will be considered a slave in all
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
Start Condition All command are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24645 continuously monitors the SDA and SCL lines for the start condition and will not respond to
applications.
any command until this condition has been met. Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
2783 ILL F04
Notes: (5) Typical values are for TA = 25C and nominal supply voltage (5V) (6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.
Figure 2. Definition of Start and Stop
SCL
SDA START BIT STOP BIT
2783 ILL F05
3
X24645
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a
read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, The X24645 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24645 will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the X24645 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24645
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
will continue to transmit data. If an acknowledge is not detected, the X24645 will terminate further data transmissions. The master must then issue a stop condition to return the X24645 to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM
TRANSMITTER
DATA OUTPUT FROM RECEIVER
START
ACKNOWLEDGE
2783 ILL F06
4
X24645
DEVICE ADDRESSING Following a start condition the master must output the address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could have up to four X24645's on the bus. The four
addresses are defined by the state of the S1 and S2 inputs. S2 of the slave address must be the inverse of
The last bit of the slave address defines the operation to be performed. When set HIGH a read operation is
selected, when set LOW, a write operation is selected.
Following the start condition, the X24645 monitors the SDA bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a correct compare the X24645 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24645 will execute a read or write operation.
WRITE OPERATIONS Byte Write
the S2 input pin. Figure 4. Slave Address
HIGH ORDER
DEVICE SELECT ADDRESS BITS
S 2
S 1
A12 A11 A10
A9
A8
R/W
For a write operation, the X24645 requires a second address field. This address field is the byte address, comprised of eight bits, providing access to any one of 8192 words in the array. Upon receipt of the byte address, the
X24645 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge
2783 ILL F07.1
The next five bits of the slave address are an extension of the array's address and are concatenated with
the eight bits of address in the byte address field, providing direct access to the whole 8192 x 8 array.
The master then terminates the transfer by generating a stop condition, at which time the X24645 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24645 inputs
are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence. Figure 5. Byte Write
S T A R T
BUS ACTIVITY: MASTER
SLAVE ADDRESS
BYTE ADDRESS
DATA
S T O P
SDA LINE
BUS ACTIVITY: X24645
S
A C K A C K A C K
P
2783 ILL F08.1
5
X24645
Page Write The X24645 is capable of a 32-byte page write operation. It is initiated in the same manner as the byte write
operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to thirty-one more bytes. After the receipt of each byte, the X24645 will respond with an acknowledge.
ISSUE START
Flow 1. ACK Polling Sequence
WRITE OPERATION COMPLETED
ENTER ACK POLLING
After the receipt of each byte, the five low order address bits are internally incremented by one. The high
order eight bits of the address remain constant. If the master should transmit more than 32 bytes prior to gen-
erating the stop condition, the address counter will "roll over" and the previously written data will be overwritten As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to
Figure 6 for the address, acknowledge, and data transfer sequence. Acknowledge Polling The Max Write Cycle Time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle, then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation.
ISSUE SLAVE ADDRESS AND R/W = 0
ISSUE STOP
ACK RETURNED?
NO
YES
NEXT OPERATION
NO
A WRITE? YES
ISSUE BYTE ADDRESS
ISSUE STOP
Refer to Flow 1.
PROCEED PROCEED
2783 ILL F09
Figure 6. Page Write
S T A R T
BUS ACTIVITY: MASTER
SLAVE ADDRESS
BYTE ADDRESS (n)
DATA n
DATA n+1
DATA n+31
S T O P
SDA LINE
BUS ACTIVITY: X24645
S
A C K A C K A C K A C K A C K
P
2783 ILL F10.2
6
X24645
READ OPERATIONS Read operations are initiated in the same manner as write operations with the exception that the R/W bit of
the slave address is set HIGH. There are three basic read operations: current address read, random read and transmits the byte. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the sequence of address, acknowledge and data transfer. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set HIGH, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address with the R/W bit set LOW, followed by the byte address it is to read. After the word address acknowledge, the master immediately reissues the start condition
and sequential read.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Current Address Read Internally the X24645 contains an address counter that maintains the address of the last byte read, incremented by one or the exact address of the last byte written. Therefore, if the last access read was to address n, the
next read operation would access data from address n + 1. Upon receipt of the slave address with the R/W
and the slave address with the R/W bit set HIGH. This will be followed by an acknowledge from the X24645 and then by the data byte. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data
set HIGH, the X24645 issues an acknowledge Figure 7. Current Address Read
S T A R T
transfer sequence.
BUS ACTIVITY: MASTER
SLAVE ADDRESS
S T O P
SDA LINE
BUS ACTIVITY: X24645
S
A C K
P DATA
2783 ILL F11
Figure 8. Random Read
S T A R T S T A R T
BUS ACTIVITY: MASTER
SLAVE ADDRESS
BYTE ADDRESS n
SLAVE ADDRESS
S T O P
SDA LINE
BUS ACTIVITY: X24645
S
A C K A C K
S
A C K
P DATA n
2783 ILL F12.1
7
X24645
Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first byte is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24645 continues to output data for each acknowledge received. The read operation is terminated by the master; by not responding with an acknowledge and then issuing a The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 8191), the counter "rolls over" to 0 and the X24645 continues to output data for each acknowledge received. Refer to Figure 9 for the address,
acknowledge and data transfer sequence.
stop condition.
Figure 9. Sequential Read
SLAVE ADDRESS
S T O P
BUS ACTIVITY: MASTER
A C K
A C K
A C K
SDA LINE
BUS ACTIVITY: X24645 A C K
P DATA n DATA n+1 DATA n+2 DATA n+x
2783 ILL F13
Figure 10. Typical System Configuration
V CC
PULL-UP RESISTORS SDA SCL MASTER TRANSMITTER/ SLAVE RECEIVER SLAVE TRANSMITTER/ MASTER TRANSMITTER MASTER TRANSMITTER/
RECEIVER
RECEIVER
RECEIVER
2783 ILL F14
8
X24645
WEL and RWEL are volatile latches that power-up in the LOW (disabled) state. A write to any address other
than 1FFFh, where the Write Protect Register is located, will be ignored (no ack) until the WEL bit is set HIGH. The WEL bit is set by writing 0000001x to address 1FFFh. Once set, WEL remains HIGH until
2 RWEL 1 WEL 0 0
WRITE PROTECT REGISTER The Write Protect Register (WPR) is located at the highest address, 1FFFh.
Figure 11. Write Protect Register
WPR (ADDR = 1FFFh) 7 WPEN 6 0 5 0 4 BP1 3 BP0
either reset (by writing 00000000 to 1FFFh) or until the part powers-up again. The RWEL bit controls writes to the block protect bits. RWEL is set by first setting WEL to "1" and then writing 0000011x to address 1FFFh. RWEL must be set in order to change the block protect bits, BP0 and BP1, or the WPEN bit. RWEL is reset
2783 ILL F15.1
WPR.1 = WEL -- "Write Enable" Latch (Volatile) 0 = Write enable latch reset, writes disabled 1 = Write enable latch set, writes enabled
when the block protect or WPEN bits are changed, or when the part powers-up again. Programming the BP or WPEN Bits A three step sequence is required to change the nonvolatile Block Protect or Write Protect Enable:
1) Set WEL = 1 (write 00000010 to address 1FFFh, volatile write cycle)
If WEL = "0" then "no ACK" after first byte of input data.
WPR.2 = RWEL -- "Register Write Enable" Latch (Volatile) 0 = Register write enable latch reset, writes disabled
1 = Register write enable latch set, writes enabled
WPR.3, WPR.4 = BP0, BP1 -- Block Protect Bits (Nonvolatile)
(Start)
2) Set RWEL = 1 (write 00000110 to address 1FFFh, volatile write cycle)
(See Block Protect section for definition)
WPR.7 = WPEN
(Start)
3) Set BP1, BP0, and/or WPEN bits (Write w00yz010 to address 1FFFh)
- Write Protect Enable Bit (Nonvolatile) (See Hardware Write Protect section for definition) Writing to the Write Protect Register The Write Protect Register is written by performing a random write of one byte directly to address, 1FFFh. If
a page write is performed starting with any address other than 1FFF, the byte in the array at address
w = WPEN, y = BP1, Z = BP0, (Stop)
Step 3 is a nonvolatile write cycle, requiring 10ms to complete. RWEL is reset to "0" by this write cycle,
requiring another write cycle to set RWEL again before the block protect bits can be changed. RWEL must be
1FFFh will be written instead of the Write Protect Register (assuming writes are not disabled by the
block protect register).
The state of the Write Protect Register can be read by performing a random read at address 1FFFh at any
"0 in step 3; if w00yz110 is written to address 1FFFh, " RWEL is set but WPEN, BP1 and BP0 are not
changed (the device remains at step 2).
time. If a sequential read starting at any other address than 1FFFh is performed, the contents of the byte in
the array at 1FFFh is read out instead of the Write Protect Register.
9
X24645
Block Protect Bits The Block Protect Bits BP0 and BP1 determine which blocks of the memory are write-protected:
Programmable Hardware Write Protect The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Write Protect Register
Table 1. Block Protect Bits
Protected Addresses None 1800h-1FFFh 1000h-1FFFh 0000h-1FFFh Upper 1/4 Upper 1/2
Full Array (WPR not included)
2783 FRM T02
control the programmable hardware write protect feature. Hardware write protection is enabled when the WP pin is HIGH and the WPEN bit is "1", and disabled when either the WP pin is LOW or the WPEN bit is "0".
When the chip is hardware write-protected, nonvolatile writes are disabled to the Write Protect Register, including the BP bits and the WPEN bit itself, as well as to block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written. Note that since the WPEN bit is write-protected, it cannot be changed back to a LOW state, and write protection is disabled as long as the the WP pin is held HIGH. Table 2 defines the write protection status for each state of
BP1
0 0 1 1
BP0
0 1 0 1
WPEN and WP. Table 2. Write Protect Status Table
Memory Array (Not Block Protected)
WP
L X H
WPEN
X 0 1
Memory Array (Block Protected) Protected Protected Protected
BP Bits
Writable Writable Protected
WPEN Bit
Writable Writable Protected
2783 FRM T03.1
Writable Writable Writable
10
X24645
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias
X24645 ....................................... -65C to +135C Storage Temperature ........................ -65C to +150C Voltage on any Pin with Respect to VSS .................................... -1V to +7V D.C. Output Current ..............................................5mA Lead Temperature (Soldering, .............................. 300C 10 seconds) RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial Military
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Min.
0C -40C -55C
Max.
+70C +85C +125C
2783 FRM T04
Supply Voltage
X24645 X24645-2.7
Limits
4.5V to 5.5V 2.7V to 5.5V
2783 FRM T05
D.C. OPERATING CHARACTERISTICS Limits Symbol
ICC1 ICC2 ISB1 (1)
Parameter
VCC Supply Current (Read) VCC Supply Current (Write) VCC Standby Current
Min.
Max.
1 3 50
Units
mA mA A
Test Conditions
SCL = VCC X 0.1/VCC X 0.9 Levels @ 100KHz, SDA = Open, All Other
Inputs = VSS or VCC - 0.3V
SCL = SDA = VCC, All Other Inputs = VSS or VCC - 0.3V,
VCC = 5V 10% ISB2 (1) VCC Standby Current 1 A
SCL = SDA = VCC, All Other Inputs = VSS or VCC - 0.3V,
VCC = 2.7V ILI ILO VlL (2) VIH (2) VOL Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage -1 VCC x 0.7 10 10 VCC x 0.3 VCC + 0.5 0.4 A A V V V IOL = 3mA, VCC = 4.5V
2783 FRM T06.2
VIN = VSS to VCC
VOUT = VSS to VCC
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V
Symbol
CI/O (3) CIN (3)
Parameter
Input/Output Capacitance (SDA) Input Capacitance (S1, S2, SCL)
Max.
8 6
Units
pF pF
Test Conditions
VI/O = 0V VIN = 0V
2783 FRM T07.1
Notes: (1)Must perform a stop command prior to measurement. (2)VIL min. and VIH max. are for reference only and are not 100% tested. (3)This parameter is periodically sampled and not 100% tested.
11
X24645
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and Fall Times Input and Output Timing Levels
EQUIVALENT A.C. LOAD CIRCUIT
VCC x 0.1 to VCC x 0.9 10ns VCC X 0.5
2783 FRM T08
5V 1.53K OUTPUT 100pF
2783 ILL F16.1
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits
Symbol
fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH
Parameter
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
Min.
0
Max.
100 100
Units
KHz ns s s s s s s s ns
SCL LOW to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
0.3 4.7 4 4.7 4
3.5
Start Condition Hold Time Clock LOW Period Clock HIGH Period
Start Condition Setup Time a Repeated Start Condition) (for
4.7 0 250 1 300 4.7 300
Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
s ns s ns
2783 FRM T09.2
POWER-UP TIMING Symbol
tPUR tPUW
(4)
Parameter
Power-up to Read Operation Power-up to Write Operation
Max.
1 5
Units
ms ms
2783 FRM T10
Notes: (4)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
12
X24645
Bus Timing
t F t HIGH t LOW t R
SCL
t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO
SDA IN
t AA t DH t BUF
SDA OUT
2783 ILL F17
Write Cycle Limits Symbol
TWR
(6)
Parameter
Write Cycle Time
Min.
Typ.
5
(5)
Max.
10
Units
ms
2783 FRM T11
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal
X24645 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not
erase/program cycle. During the write cycle, the Bus Timing
respond to its slave address.
SCL
SDA
8th BIT WORD n
ACK
t WR
STOP CONDITION
START CONDITION
2783 ILL F18
Notes: (5)Typical values are for TA = 25C and nominal supply voltage (5V). (6)tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120
RESISTANCE (K)
V R MIN
SYMBOL TABLE
WAVEFORM INPUTS
Must be steady May change from LOW
OUTPUTS
Will be steady Will change from LOW
100 80 60 40 20 0 0
=
CC MAX I OL MIN t R C BUS
=1.8K
R MAX
=
MAX. RESISTANCE
to HIGH
May change from HIGH
to HIGH
Will change from HIGH
to LOW
MIN. RESISTANCE
to LOW
Changing: State Not
Don't Care: Changes
Allowed
Known
Center Line is High
20
40
60
80100120
2783 ILL F19
N/A
BUS CAPACITANCE (pF)
Impedance
13
X24645
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10)
PIN 1 INDEX PIN 1
0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL
SEATING PLANE
0.145 (3.68) 0.128 (3.25)
0.150 (3.81) 0.125 (3.18)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14)
0.110 (2.79) 0.090 (2.29)
0.020 (0.51) 0.016 (0.41)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
14
X24645
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00)
0.228 (5.80) 0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0.050" TYPICAL
0 - 8
0.0075 (0.19) 0.010 (0.25)
0.050" TYPICAL
0.250"
0.016 (0.410) 0.037 (0.937)
0.030" TYPICAL
FOOTPRINT
8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
15
X24645
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00)
0.228 (5.80) 0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35) 0.020 (0.51)
0.336 (8.55) 0.345 (8.75)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.10) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0.050" Typical
0 - 8
0.0075 (0.19) 0.010 (0.25)
0.050" Typical 0.250"
0.016 (0.41) 0.037 (0.937)
FOOTPRINT
0.030" Typical 14 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F10.1
16
X24645
PACKAGING INFORMATION
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .177 (4.5)
.252 (6.4) BSC
.252 (6.4) .300 (6.6)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8
.019 (.50) .029 (.75)
Seating Plane
Detail A (20X)
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F45
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X24645
ORDERING INFORMATION X24645 Device P T G -V VCC Range Blank = 5V 10% 2.7 = 2.7V to 5.5V G = RoHS Compliant Lead Free package Blank = Standard package. Non lead free
Temperature Range Blank = 0C to +70C
I = -40C to +85C M = -55C to +125C
Package P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC (JEDEC) S = 14-Lead SOIC V = 20-Lead TSSOP Part Mark Convention X24645 XG
P = 8-Lead Plastic DIP S = 14-Lead SOIC Blank = 8-Lead SOIC (JEDEC) V = 20-Lead TSSOP G = RoHS compliant lead free Blank = 4.5V to 5.5V, 0C to +70C I = 4.5V to 5.5V, -40C to +85C
X
F = 2.7V to 5.5V, 0C to +70C G = 2.7V to 5.5V, -40C to +85C
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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